module common_ram_2r1w #(
    parameter ADDR_WIDTH = 8,
    parameter DATA_WIDTH = 4,               // Unit: Byte (not bit)
    parameter DEPTH      = 1 << ADDR_WIDTH
) (
    input  logic                    clk,
    // Write port
    input  logic                    wr_en,
    input  logic [  ADDR_WIDTH-1:0] wr_addr,
    input  logic [DATA_WIDTH*8-1:0] wr_data,
    input  logic [  DATA_WIDTH-1:0] wr_byte_mask,  // Byte write enable mask
    // Read port 0
    input  logic                    rd0_en,
    input  logic [  ADDR_WIDTH-1:0] rd0_addr,
    output logic [DATA_WIDTH*8-1:0] rd0_data,
    // Read port 1
    input  logic                    rd1_en,
    input  logic [  ADDR_WIDTH-1:0] rd1_addr,
    output logic [DATA_WIDTH*8-1:0] rd1_data
);

    // Declare the RAM variable
    logic [DATA_WIDTH*8-1:0] ram[0:DEPTH-1];

    // Synchronous write operation with byte mask
    always_ff @(posedge clk) begin
        if (wr_en) begin
            for (int i = 0; i < DATA_WIDTH; i++) begin
                if (wr_byte_mask[i]) begin
                    ram[wr_addr][i*8+:8] <= wr_data[i*8+:8];
                end
            end
        end
    end

    // Synchronous read operation for port 0
    always_ff @(posedge clk) begin
        if (rd0_en) begin
            rd0_data <= ram[rd0_addr];
        end
    end

    // Synchronous read operation for port 1
    always_ff @(posedge clk) begin
        if (rd1_en) begin
            rd1_data <= ram[rd1_addr];
        end
    end

endmodule
